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Software-Based Self-Test of processor-based systems: state-of-the-art and emerging trends

Date: September 27 (Tuesday)

Time: 11:00-13:00

Place: IT-209 (Raja 15, Tallinn)

 

Software-Based Self-Test of processor-based systems: state-of-the-art and emerging trends

by prof. Matteo Sonza Reorda (http://www.cad.polito.it/~sonza/). Matteo is the leader of the CAD Group working within the Dipartimento di Automatica e Informatica of the Politecnico di Torino (Italy).

 

Abstract:

The idea of testing a processor or a processor-based system (no matter whether it corresponds to a single device, a board, or whatever else) by running a proper program in charge of stimulating the different modules and observing their behavior (known as functional test, or Software-Based Self-Test, or SBST), is not new, and has been adopted in industry and investigated by researchers since several decades.

However, in the last years there has been a growing interest for this approach, and its adoption in industry seems generally increasing, while a number of papers appeared at conferences and on journals on this topic. The reasons for this are manifold, and include the following:

* Deep-submicron delay defects become more and more important, increasing the need for at-speed testing: SBST matches this constraint

* The increasing working frequency of many processors and systems, as well as of many I/O interfaces, tends to dramatically increase the cost for the Automatic Test Equipment (ATE) required for their test: SBST has very little requirements in terms of external support during test (e.g., for test programs uploading and responses downloading)

* Multicore processor and system architectures raise growing issues in terms of test time: by adopting a suitable scheduling of test program execution on different cores, SBST can easily support parallelism during the test phase of these systems, thus reducing test time upscaling

* OEM companies often need to perform some sort of incoming inspection test without having the possibility of exploiting Design for Testability (DfT) features possibly included in the device/system by the manufacturer; in other cases, on-line test requires performing some form of test when the device/system is already in the field, and again the access to the internal DfT structures may be unfeasible; SBST may allow testing a product without resorting to any internal DfT feature (or to very limited ones)

* The stimuli generated adopting the SBST paradigm are often re-used in different phases of the product design, manufacturing, and life cycle, ranging from design validation to post-silicon debug, from high-volume manufacturing test to on-line test, thus further contributing to reduce the overall costs.

The presentation aims first at summarizing what SBST is and which is the state-of-the-art in the area, secondly at identifying the main criticalities in its practical adoption, and finally at showing the major trends and research activities related to it.