3.1. Test program generation for systems.
High-Level Decision Diagram (HLDD) high level model was developed which allowed to formalize high-level test program synthesis for digital systems incl. microprocessors, and to develop new algorithms which allowed to increase fault coverage compared to the known methods.
The novelty of the proposed approach is in targeting high-level variables as test objectives, instead of testing the instructions as in the traditional case, allowing increase the quality of test and diagnostic resolution. A novel subclass of hard-to-test faults called “added unintended actions” was introduced, which are not handled by current methods. Because of cyclical organization of test procedures, the whole test program will be compact and uniform. Experimental results demonstrated higher fault coverage compared to the published results.
Cooperation: Brandenburg Technical University
PhD student: Artjom Jasnetski (expected defence 2017 )
1. Jasnetski, Artjom; Raik, Jaan; Tsertov, Anton; Ubar, Raimund. New Fault Models and Self-Test Generation for Microprocessors using High-Level Decision Diagrams. Proceedings of IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade, Serbia, April 22-24, 2015.
3.2. Aging and reliability of systems
One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI), which may result in failures in the circuits due to delaying of signals. A novel approach was proposed to identify NBTI-critical paths in circuits that is based on analyzing the combination of three parameters: delay-critical paths, gate input signal probabilities and gate fan-out degrees along the paths. The identified NBTI-critical paths can be used e.g. for inserting of aging sensors, rejuvenation stimuli generation, etc. A new method for generating rejuvenation sequences for CMOS Integrated Circuits using evolutionary algorithms was developed.
Cooperation: Politecnico di Torino, Pontifical Catholic University of Rio Grande do Sul (PUCRS) Brasil, University of Technology Liberec, Czech Republic
PhD student: Valentin Tihhomirov (expected defence in 2016)
1. Palermo, N.; Tihhomirov, V.; Copetti, T.S.; Jenihhin, M.; Raik, J.; Kostin, S.; Gaudesi, M.; Squillero, G.; Sonza Reorda, M.; Vargas, F.; Bolzani Poehls, L. (2015). Rejuvenation of Nanoscale Logic at NBTI-Critical Paths Using Evolutionary TPG. 16th IEEE Latin-American Test Symposium March 25 - 27, 2015, Puerto Vallarta, Mexico (1 - 6).IEEE Computer Society Press
2. Kostin, Sergei; Raik, Jaan; Ubar, Raimund; Jenihhin, Maksim; Copetti, Thiago; Vargas, Fabian; Bolzani Poehls, Leticia (2015). SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2015, Belgrade, Serbia (1 - 6).IEEE Computer Society Press
3.3. Concurrent on-line test for Networks-on-Chip
Network on Chips (NoCs) are composed of routers, whose task is to dispatch packets within the communication network according to the routing algorithm implemented. However, the extreme scaling of emerging nanometer technologies makes the routers vulnerable to wear-out and environmental effects. In order to contain this issue, development of online testing capabilities for the NoC routers is a must. This work proposes concurrent online checkers for structural faults in the NoC routing algorithms utilizing the Logic-Based Distributed Routing (LBDR) concept. We show by fault injection experiments that the fault coverage of existing checking mechanisms for LBDR faults is very low. We propose an extended set of concurrent checkers that increase the coverage more than threefold facilitating detection of the majority of structural faults within the LBDR.
PhD students: Behrad Niazmand, Ranganathan Hariharan (joined CEBE in 2014)
1. Niazmand, Behrad; Hariharan, Ranganathan; Govind, Vineeth; Jervan, Gert; Hollstein, Thomas; Raik, Jaan (2014). Extended Checkers for Logic-Based Distributed Routing in Network-on-Chips. Baltic Electronic Conference, Laulasmaa, Estonia (1 - 4).IEEE
2. Hariharan, Ranganathan; Niazmand, Behrad; Hollstein, Thomas; Raik, Jaan; Jervan, Gert (2015). Extended Checkers for Control Part of Routers in Network-on-Chips. MEDIAN Workshop (1 - 6).EU COST
3.4. Fault management and fault-tolerance.
Fault tolerance and fault management mechanisms (FMA) are necessary means to reduce the impact of soft errors and wear out in electronic devices. Typically, fault tolerance techniques assume certain limits in error rates when they are still applicable. Failure resilience goes beyond that by localizing and classifying faults into transient vs. permanent and critical vs. low-priority ones. We have proposed a new general scalable fault management architecture based on the latest upcoming DFT standard IEEE P1687 IJTAG . The architecture allows efficient handling of fault detection information as well as to manage test and system resources as a system-wide background process during system operation.
Novel methods for reducing fault detection latency and the time required for faulty resource localization have been proposed, which includes a formula for assessing the worst-case number of TCK cycles needed to perform fault diagnosis.
1. Jutman, Artur; Devadze, Sergei; Shibin, Konstantin (2013). Effective Scalable IEEE 1687 Instrumentation Network for Fault Management. IEEE Design & Test of Computers, 30 (5), pp. 26-35.
2. Shibin, Konstantin; Jutman, Artur; Devadze, Sergei (2013). Fault Management Instrumentation Network based on IEEE P1687 IJTAG. 18th IEEE European Test Symposium (PhD student work-in-progress Papers), May 27-31, 2013. IEEE Computer Society.