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2. Verification and diagnosis

2.1. Diagnostic modeling of digital systems

Graph-based system modeling. A novel shared SSBDD (S3BDD) logic model was developed for representing the structure of digital circuits to give a possibility of direct modeling of the internal faults of circuits.

The new model made it possible to achieve several important practical results in high macro-level fault simulation with low gate-level accuracy: (a) to reduce the complexity of the previous BDD models, (b) to speed up simulation for both combinational and sequential circuits, and (c) to improve the known methods of fault collapsing both, in speed-up, and in the number of collapsed faults.

The new fault collapsing method [1] based on S3BDDs outperforms the known methods in the speed, since the algorithm has a linear complexity.

Multiple-fault modeling. Traditional approaches in testing of digital systems are based on assumption of the presence of single faults. The first time, a novel idea of test groups [2] was introduced to cope with the problem of possible multiple fault mutual masking. A method was developed for generating test groups to avoid fault masking by proving step by step the correctness of continuously increased sub-circuits.

Cooperation: Brandenburg Technical University

PhD student: Dmitri Mironov (Expected defence in 2015)

Publications:

1.      D.Mironov, R.Ubar. Logic Simulation and Fault Collapsing with Shared Structurally Synthesized BDDs. IEEE European Test Symposium, Paderborn, Germany, May 26-30, 2014.

2.      R.Ubar (2013). Boolean Fault Diagnosis with Structurally Synthesized BDDs. In “Recent Progress in the Boolean Domain”, Edited by Bernd Steinbach. Cambridge University Press, pp.302-331.

 

2.2. Fault simulation

Stuck-at-fault simulation.  A novel very fast parallel fault simulation method was developed, based on exact critical path reasoning in digital circuits [1,2].

The method exploits the first time concurrently two types of parallelism: bit-level parallelism for multiple pattern reasoning, and algorithmic level parallelism for distribution of the reasoning process between different cores in a multi-core processor environment. To increase the speed and accuracy of fault simulation, compared with previous methods, in addition, a mixed level fault reasoning approach was developed.

The method has been successfully used for evaluation of on-line functional test quality of signal processing systems with very long test lengths (up to 80 000 clock-cycles).

Delay fault simulation. A new method was developed for simulating of transition delay faults (TDF) at different fault propagation conditions [3]. The main idea of the method is to extend the TDF model, traditionally considered as a class of robustly tested delay faults, to a broader class of TDFs with four different detection conditions. A novel sequential 7-valued algebra was developed for TDF reasoning.

The new method allows higher accuracy of transition delay fault coverage calculation compared to the known methods.

PhD students: Maksim Gorev (expected defence in 2015), Jaak Kõusaar (expected defence in 2017)

Implementation:  Prototyps of parallel fault simulator and delay fault simulator

Publications:

1.      M.Gorev, R.Ubar, S.Devadze. Fault Simulation with Parallel Exact Critical Path Tracing in Multiple Core Environment. Proceedings of IEEE Conference on Design, Automation & Test in Europe – DATE-2015, Grenoble, France, 9-13 March, 2015, pp. 1-6.

2.      M.Gorev, R.Ubar, P.Ellervee, S.Devadze, J.Raik, M.Min. Functional Self-Test of High-Performance Pipe-Lined Signal Processing Architectures. J. of Microprocessors and Microsystems. Available online 15 November 2014 (In Press). 

3.      J.Kõusaar, R.Ubar, S.Devadze, J.Raik. Critical Path Tracing based Simulation of Transition Delay Faults. The EUROMICRO Conference on Digital System Design – DSD, Verona, Italy, Aug. 27-29, p. 1-6.

 

2.3. Hardware verification and debugging

Design error diagnosis. A new scalable method for bug localization within a processor design project was developed [1]. The both methods were implemented on top of a highly scalable HDL-centric open source hardware design and debugging framework zamiaCAD, developed recently in the international cooperation by the research team. The case study has been carried out on a real processor design ROBSY.

The main contribution of this approach compared to the  State-of-the-Art is, first, combining statistical analysis with HDL slicing, second, performing hierarchical localization in statements, branches and conditions of the code and, third, developing an efficient cone inspection technique in concurrent HDL descriptions.

A new method for assessment of diagnostic tests for automated hardware bugs localization was proposed [2].  The method provides a measure of confidence in localization results and allows to estimate the impact of test on the quality of diagnosis.

The first time an approach was developed for diagnostic test generation for statistical bug localization using evolutionary computation. The new approach significantly saves test generation time by avoiding experiments for each bug to be carried out iteratively during the evolutionary optimization process. Second, it supports reuse of the test set in case of later modifications to the code.

The method was used for a Plasma processor and the results showed significantly improved diagnostic resolution of localizing design bugs by the test generated by the proposed approach.

Automated design repair. A new method for locating design errors in RTL designs using HLDD models and correcting them by applying mutation operators was developed [3].

Differently from the current methods, which are based on reducing the debugging problem to SAT or SMT solvers, but which is an NP-complete problem, the proposed new approach utilizes a novel HLDD based back-tracing idea which executes in polynomial time. This means that much larger designs could be handled by the proposed method.

Experiments on a set of sequential RTL benchmarks showed that the new mutation-based correction method is capable of locating design errors with high accuracy, requires very small number of iterations and thus is characterized by a short run-time. The engine operates on the register-transfer level, hence gives a well readable diagnostic feedback and is therefore better understandable to the engineer than logic-level debug information provided by previous methods.

Cooperation:  TU Ilmenau, zamiaCAD (Germany), Politecnico di Torino (Italy)

PhD Thesis:  Anton Tchepurov (2013)

PhD students: Hanno Hantson (expected defence in 2015), Valentin Tihhomirov (expected defence in 2016)

Implementation: Prototype tool for design error diagnosis and for automated design repair.

Publications:

1.      M.Jenihhin, Anton Tšepurov, Valentin Tihhomirov, J.Raik, Hanno Hantson, R.Ubar, Günter Bartsch, Jorge Hernan Meza Escobar, Heinz-Dietrich Wuttke (2014). Automated Design Error Localization in RTL Designs. J. of IEEE Design & Test, Vol.1, pp. 83-92.

2.      Marco Gaudesi,  Maksim Jenihhin,  Jaan Raik,  Ernesto Sanchez,  Giovanni Squillero,  Valentin Tihomirov,  Raimund Ubar. Diagnostic Test Generation for Statistical Bug Localization using Evolutionary Computation. Applications of Evolutionary Computation Lecture Notes in Computer Science 2014,   pp 425-436.

3.      Raik, Jaan; Repinski, Urmas; Tšepurov, Anton;  Hantson, Hanno; Ubar, Raimund; Jenihhin, Maksim. (2013). Automated design error debug using high-level decision diagrams and mutation operators. J. of Microprocessors and Microsystems, 37(4), pp. 505-513.

2.4. Abstraction of RTL designs to ESL

The rapid increase of embedded systems design complexity has resulted in emergence of design methodologies at higher levels of abstraction such as Electronic System Level (ESL) and Transaction Level Modeling (TLM) with SystemC language as the main instrument. In practice, system architects and system integrators often have access to a library of legacy Register Transfer Level (RTL) IP (Intellectual Property) cores or obtain new ones from IP design houses. To address architectural exploration, early prototyping and simulation performance, such RTL IP cores are manually recreated at more abstract levels, which implies significant and error-prone effort. This work proposes an approach for automated abstraction of the computational part of cycle-accurate RTL IP cores to untimed TLM using a novel concept of SystemC-based Loose Models (SCLM). SCLMs provide for an instrument to neglect design model parts irrelevant for particular manipulation step of the abstraction process, thus simplifying the abstraction flow. As a result, the computational complexity of the abstraction process is reduced, thus increasing the overall scalability. The proposed abstraction flow is demonstrated on a set of benchmark designs and the first experimental results prove feasibility of the proposed approach and also show considerable simulation speed-up.

Cooperation:  IBM (India)

PhD student: Saif Syed Abrar (expected defence in 2015)

Implementation: Extensions to open source framework zamiaCAD

Publications:

1.      Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan (2015). SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2015, Belgrade, Serbia (1 - 4).IEEE Computer Society Press