1.1 Design of dependable multi-core systems
A new design environment for analysis, modelling and synthesis of NoC-based many-core systems has been developed. The main results:
• Generalized communication modelling and synthesis framework for calculation of the communication latency in NoC-based hard real-time systems. The framework enables task partitioning and scheduling for improving the efficiency of the resulting system, without compromising the deadlines.
• Framework for analyzing the impact of transient failures on real-time applications and methodology for improving the fault tolerance through timing redundancy. The objective is to guarantee the deadlines in fault-prone environments. The approach has been also extended to applications with multiple levels of criticality.
Cooperation: TU Darmstadt (Germany)
PhD thesis: Mihkel Tagel (2012)
Implementation: System-level design environment for timing-sensitive network-on-chip based dependable systems
1. Tagel, Mihkel, Ellervee, Peeter, Jervan, Gert (2009). Scheduling Framework for Real-time Dependable NoC-Based Systems. International Symposium on System-on-Chip 2009 (95 - 99).
2. Tagel, M.; Ellervee, P.; Jervan, G. (2011). System-Level Design of NoC-Based Dependable Embedded Systems. Ubar, R.; Raik J.; Vierhaus, H. T. (Eds.). Fault-Tolerance and Applications in System-on-Chip Design: Advancements and Techniques (1 - 36). Hershey, Pennsylvania, USA: IGI Global
3. Tagel, M.; Ellervee, P.; Hollstein, T.; Jervan, G. (2011). Communication modelling and synthesis for NoC-based systems with real-time constraints. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems 2011 (237 - 242)
4. Amin, M.; Tagel, M.; Jervan, G.; Hollstein, T. (2012). Design Methodology for Fault-tolerant heterogeneous MPSoC under Real-Time Constraints. 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (1 - 6).
5. Bagheri, Mehrdad; Jervan, Gert (2014). Fault-tolerant scheduling of mixed-critical applications on multi-processor platforms. 2014 IEEE International Conference on Embedded and Ubiquitous Computing pp. 25 - 32.
1.2. Dependable 3D NoC Architectures
Implementation of a novel concept (NoCDepend) beyond the state-of-the-art for being capable to cope with any amount of communication infrastructure faults in Networks-on-Chip. This allows nearly 100% use of NoC architectures independent of the amount of static faults in the routing network. The method is scalable and can be combined with any adaptive and even non-minimal NoC routing algorithm in 2D and 3D networks. The method additionally provides the potential for resource partitioning on MPSoC platforms for mixed criticality application scenarios. The integration into the GSNoC NoC Simulator has been implemented and validations have been carried out by simulation. The current method is generalistic and a universal method for proving of the deadlock-freeness of any NoC routing model has been developed and implemented. The dependability layer will be used as basis for mixed-criticality application deployment in ongoing research.
Furthermore, in cooperation with TU Darmstadt, adaptive routing algorithms have been researched successfully for 3D Networks-on-Chip, which assume sparse vertical router links via Trough-Silicon-Vias (TSVs) and which are additionally adaptive and deadlock-free.
PhD students: Siavoosh Payandeh Azad (expected defense in 2018); Haoyuan Ying (TU Darmstadt, defended in 2014);
Implementation: GSNoC simulator; 3D adaptive routing; dependability overlay implemented in GSNoC in combination with the XHiNoC NoC architecture
1. Thilo Kogge: Graph-based Methods for Property Evaluation of On-Chip Routing Algorithms and Implementation of a scalable Network-on-Chip Dependability Layer; Bachelor Thesis in cooperation with TU Darmstadt; to be published in Mai 2015
2. Thomas Hollstein, Siavoosh Payandeh Azad, Thilo Kogge, Haoyuan Ying, Klaus Hofmann: NoCDepend: A flexible and scalable DependabilityTechnique for 3D Networks-on-Chip; IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2015, Belgrade, Serbia, accepted
3. Ying, Haoyuan; Hofmann, Klaus; Hollstein, Thomas (2014). Dynamic quadrant partitioning adaptive routing algorithm for irregular reduced vertical link density topology 3-Dimensional Network-on-Chips. 2014 International Conference on High Performance Computing & Simulation (HPCS). , 516 - 522
4. Ying, Haoyuan; Hollstein, Thomas; Hofmann, Klaus (2014). A hardware/software co-design reconfigurable Network-on-Chip FPGA emulation method. 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014, 1 - 8.
5. Haoyuan Ying, Thomas Hollstein, Klaus Hofmann (2013). GSNoC — The comprehensive design platform for 3-dimensional Networks-on-Chip based many core embedded systems . International Conference on High Performance Computing and Simulation (HPCS), pp. 217 – 223, 1-5 July 2013, doi: 10.1109/HPCSim.2013.6641417.
6. Haoyuan Ying, Thomas Hollstein, Klaus Hofmann: Fast and Optimized Task Allocation Method for Low Vertical Link Density 3-Dimensional Networks-on-Chip Based Many Core Systems, in: Proc. of the DATE Conference 2013, S.1777- 1782, März 2013, Grenoble, France
1.3. Coarse grained reconfiguration
Coarse grained reconfigurable architectures targeting distributed massive parallel signal processing algorithms were developed in cooperation with Royal Institute of technology, Sweden, and Turku University, Finland . The novelty of the solution is in the way the coarse grained architectures are programmed – algorithms are parallelized and distributed between processing units by modifying relative addressing inside programs when transferring program code from one unit to another. This allows to reduce configuration and programming overheads thus in addition of speeding up calculations energy is also saved.
A design environment (GSNoC) for fast and cycle accurate simulation of 3D NoC systems with regular or sparse vertical links has been set up, in order to provide a quick validation of task mapping and scheduling methods. Furthermore, new adaptive routing methods on 3D NoCs have been developed .
Cooperation: Royal Institute of technology, Sweden, and Turku University, Finland.
1. Jafri, S.M.A.H.; Tajammul, M.A.; Ellervee, P.; Hemani, A.; Paul, K.; Tenhunen, H.; Plosila, J. (2014). Morphable Compression Architecture for Efficient Configuration in CGRAs. The 17th Euromicro Conference on Digital System Design (DSD 2014), Verona, Italy, Aug. 2014 , 42 - 49.
2. Bagheri, Mehrdad; Jervan, Gert (2014). Fault-tolerant scheduling of mixed-critical applications on multi-processor platforms. 2014 IEEE International Conference on Embedded and Ubiquitous Computing pp. 25 - 32.
1.4. Hardware/software co-design
Analysis and comparison of attainable hardware acceleration in All Programmable Systems-on-Chip (Zynq-7000 based) was conducted. Such devices permit complete solutions for embedded systems to be integrated on a chip. We studied interaction mechanisms for data transfer which involve communication overheads that have to be taken into account in any hardware/software system. Thorough evaluation of the available on-chip high-performance interfaces is done based on the results of numerous experiments. Two types of projects that are data sorters and popcount computations were chosen for particular assessments. We found that efficiency of software/hardware solutions depends on many mutually related factors such as the volume of processed data, applied parallelism, and involved high-performance ports.
Cooperation: U Aveiro (Portugal)
1. V. Sklyarov, I. Skliarova, J. Silva, A. Rjabov, A. Sudnitson, C. Cardoso. Hardware/Software Co-design for Programmable Systems-on-Chip. TUT Press, Tallinn, 2014, 306 p., ISBN: 978-9949-23-625-1.
1.5. Networked Embedded and Cyberphysical Systems: R&D Platform
In order to come up with a directed design and optimization approach for embedded healthcare applications, within the project a generic design platform has been developed. It allows design approaches and research on design optimization with respect to power consumption, performance and fault-tolerance outgoing from virtual prototypes. The analysis of the system can be decomposed systematically and functionality test and reliability analysis can be applied on the design hierarchy going along with research results in the field of built-in self-test (BIST), dependable system design and power/performance optimization.
Figure 1: Directed Design Process
Figure 1 depicts the design process: Based on existing templates a virtual prototyping can be carried out, resulting in system-level design implementation decisions. The evaluation of design alternative on system-level is carried out based on a cost function, considering the properties of different design templates in the IP component database.
The generic platform architecture is shown in Figure 2. In the Smart Personal Environment, locally communicating smart sensor/actuator nodes are collecting data or providing stimulation to the biological system. Typically these devices are battery-driven and a long battery lifetime is desirable here. Depending on the computational requirements (data pre-processing), different alternatives can be considered here: microcontrollers and ASICS (low power) or DSPs/GPPs in case of need of increased computing performance. Feasible communication standards can be 6loWPAN or Bluetooth on this level.
Figure 2: Generic Platform Architecture
The local sensor network is connected to the next higher abstract layer, which is defined by the Smart In-house infrastructure. On this level data is aggregated, analyzed and processed. Here partially existing infrastructure can be used like mobile phones for aggregation and processing and WLAN/Blutooth as communication infrastructure. The whole two-layer front-end can be connected via secured internet connection to data services and tele-medicine services, which allow medical doctors to be in interaction with the patient and have a quick review of the acquired data and extracted properties/symptoms.
1. Le Moullec, Y.; Lecat, Y.; Annus, P.; Land, R.; Kuusik, A.; Reidla, M.; Hollstein, T.; Reinsalu, U.; Tammemäe, K.; Ruberg, P. (2014). A Modular 6LoWPAN-based Wireless Sensor Body Area Network for Health-Monitoring Applications. Asia-Pacific Signal and Information Processing Association Annual Summit and Conference 2014.